The invention relates to an integrated circuit comprising a programmable cell provided with a programmable element having a first conductive layer, a second conductive layer and a dielectric layer arranged between them, while the cell can be programmed by producing in the dielectric layer an electric breakdown, as a result of which the programmable element passes permanently from an electrically non-conducting state to an electrically conducting state.
It is known to use programmable cells in electronic cards (smart cards), such as, for example, electronic credit cards. These cards are generally cards made of synthetic material, in which a semiconductor device having a storage capacitance and, as the case may be, a microprocessor is embedded. Especially in recent years, such cards have been used more and more frequenctly for, for example, electronic funds transfer and protection purposes. Coding keys and other data can be stored in the memory, which regulate reading and writing from and to the card. For safety considerations, given coding keys should be non-erasable. In fact, by erasing, the card could be brought back into a state allowing new keys and data to be programmed.
Non-erasable programmable cells are often provided with safety fuses. These safety fuses are conductor tracks, in which a restriction is locally provided. The safety fuse is programmed by conducting an electric current through the track in such a manner that the safety fuse melts at the area of the restriction or oxidizes, as, for example, in a safety fuse of silicon, as a result of which the safety fuse passes from an electrically conducting state to a non-conducting state. However, the use of such elements has a number of disadvantages. For example, the written information is visible, as a result of which it is possible to read the secret coding keys and data from the card, for example under a microscope. Moreover, safety fuses have the disadvantage that the programming currents required for melting the safety fuse are considerably larger than the usual operating currents in semiconductor devices. The supply of these large currents requires comparatively large selection transistors, which increase the volume and the cost of the device and moreover delay the access to the memory.
A circuit of the kind mentioned above is known from European Patent Application No. 213,638. This known circuit comprises a memory matrix composed of a large number of programmable cells. Each cell comprises a field effect transistor, a gate electrode of which is connected to a word line. Each cell further comprises an element of the kind mentioned in the opening paragraph, of which one of the conductive layers is connected to the transistor and the other conductive layer is connected to a bit line. The cell can be programmed by producing an electric breakdown in the dielectric layer, as a result of which the programmable element permanently passes from an electrically non-conducting state to an electrically conducting state.
Fairly complicated and voluminous additional circuits are required for reading and writing information into the known circuit and for selecting bit and word lines.
For large memories this is not an unsurmountable objection because the volume of these circuits is small as compared with the volume of the actual memory. For comparatively small memories, however, the use of the known circuit would result in that the memory would have to be provided with additional circuits, which occupy a comparatively large amount of space as compared with the actual memory. This disadvantage is even greater when a number of small memories or even individual programmable cells are distributed over the semiconductor device. Moreover, an output signal of a programmable cell often can not be directly processed in digital form in the known circuit. For this purpose, it should often first be shaped into a suitable form, which requires an additional circuit.